1. Field of the Invention
The present invention relates to a VCO circuit using a digital VCO, a PLL circuit using the VCO circuit, a data recording apparatus using the PLL circuit.
2. Description of the Related Art
A conventional data recording apparatus carries out recording and reproducing processes of data to recording media such as optical discs, e.g., CD-R and DVD-R/RW. Such a conventional data recording apparatus acquires a rotation synchronous signal from the recording medium and extracts a synchronous clock signal based on the rotation synchronous signal to use the synchronous clock signal as a record clock signal in the recording and reproducing processes.
Generally, a PLL (phase Locked loop) circuit is used for the extraction of such a periodical clock signal. Moreover, the PLL circuit can be used for various purposes in addition to the purpose of reproduction and extraction of the synchronous clock signal. The PLL circuit includes a VCO (Voltage Controlled Oscillator). The VCO converts the level of an input signal into an oscillation frequency, i.e., outputs an oscillation signal with a frequency corresponding to the input signal level. The PLL circuit outputs the synchronous clock signal with the input signal by controlling the phase of the signal outputted from the VCO.
An analog VCO has a large manufacturing process dependent deviation in input-output characteristics and a high temperature dependence. Therefore, the output of the analog VCO is generally stabilized by using a PLL loop. For this reason, a digital VCO is used, when the PLL circuit characteristic influences the performance of the data recording apparatus using the PLL circuit, when a broadband oscillation signal should be necessary, or when the deviation in characteristic of the PLL circuit should be suppressed in an LSI. The digital VCO has various advantages such as the linearity of an input/output signal in a wide range, small deviation in input-output characteristics, and easy manufacturing of the LSI.
In the digital VCO, it is supposed that the frequency of the output oscillation signal from the digital VCO is F and the frequency of a reference clock signal is Fref. In this case, a frequency control input is phase difference data expressed by bits in case of the PLL circuit (containing a case of a signal filtered by a filter) and is supplied to the digital VCO as digital data. The output of the digital VCO is a pulse signal or a clock signal with an oscillation frequency corresponding to the frequency control input.
An output period resolution or output frequency resolution of the digital VCO is determined in accordance with the frequency Fref of the reference clock signal used to drive the digital VCO. For example, when the frequency F of the oscillation signal to be generated is coincident with Fref/N (N is a natural number), it is possible for the digital VCO to oscillate correctly at a desired frequency. However, when the digital VCO should oscillate at a desired frequency between Fref/N and Fref/(N+1), it is not possible for the digital VCO to oscillate correctly at the desired frequency. In such a case, it is necessary to output a clock signal with the period of N/Fref and a clock signal with the period of N+1/Fref at a predetermined rate. By outputting such clock signals with the different periods at the predetermined rate, the clock signal with the desired frequency can be outputted.
However, a phase shift or a phase error exists between the desired clock signal and the actually outputted clock signal at each clock timing. This produces a spurious band. This spurious band causes jitter. Therefore, it is desirable to restrain the generation of the spurious band as much as possible, namely, to output the clock signal with the desired output timings. For this purpose, it is necessary to improve the phase resolution of the VCO in the PLL circuit.
In the conventional digital PLL circuit, the frequency of the reference clock signal must be made high for the improvement of the resolution. However, there is a limit in the operation frequency of an adder of the digital VCO. When the frequency of the reference clock signal is made high, the reference clock signal is easy to undergo influence of noise and the waveform of the reference clock signal is distorted not to keep the pulse shape. As a result, the operation of a logic circuit becomes instable. Also, because the adder outputs a calculation result at the timing synchronized with the reference clock signal, the phase precision is not always improved.
Also, in the data recording apparatus which carries out a data recording process in response to a record clock signal generated by the PLL circuit using the VCO, it is not possible to sufficiently reduce clock jitter at a high-speed operation. As a result, it is difficult to accomplish high record quality.
A VCO circuit, a PLL circuit and a data recording apparatus are disclosed in Japanese Laid Open Patent Application (JP-P2003-209468A). In this conventional example, a phase error data with a resolution finer than the period of an output clock signal is outputted at a same timing as that of the output oscillation signal. Phase modulation is carried out at an edge timing of the output oscillation signal of the digital VCO based on the phase error data so as to shift the spurious band to a band apart from the frequency band of the output oscillation signal. Thereafter, the sifted spurious band is cut using a band pass filter (BPF). Thus, a clock signal with few jitters is outputted.
However, the above conventional example does not reduce the absolute value of intensity of a signal at the spurious band. That is, the generation of the spurious band itself is not suppressed. Therefore, there is a fear that jitter is generated due to the spurious band in the band apart from the fundamental frequency of the reference clock signal.
In this way, in the conventional technique, the VCO cannot control the output timing of a clock signal finer than the period of a reference clock signal. Also, the generation of a phase error itself or the generation of the spurious band cannot be reduced.